Generation of nanosecond pulses is important for electromagnetic (EM) telecommunications (e.g., radar or microwave), lasers and other applications. The pulse shape can be bell or step-shaped, among others. The power, repetition frequency and rise time of the pulse, however, are more important characteristics than its shape in EM telecommunications. Voltage is preferably on the order of 100 volts (V) or higher and depends on frequency. Rise time is preferably 1.0 nanosecond (ns) or less. Step recovery devices (SRDs) have been employed in efforts to achieve these types of pulses. Current SRDs have achieved 1-2 ns rise times, but pulse repetition frequencies are too low. Further, frequencies of greater than 20 Megahertz (MHz) have been achieved with SRDs, but pulse power has been insufficient. Further, SRDs have been acknowledged to have thermal stability problems.
A paper entitled "Fast Power Switches From Picosecond to Nanosecond Time Scale and Their Application to Pulsed Power" by A. F. Kardo-Syssoev et al of the Ioffe Physico-Technical Institute, Academy of Science, St. Petersburg, Russia, addresses super fast voltage restoration and super fast reversible delayed breakdown effects in high voltage semiconductor p-n junctions discovered at the Ioffe Institute and drift step recovery (DSR) devices and silicon avalanche shapers (SASS) exhibiting these effects. In contrast with an SRD, a drift step recovery diode (DSRD) is designed with a particular doping profile of p-layer (i.e., a p-layer consisting of both a heavily doped portion and a lower doped portion) and uses a pulse as opposed to a DC signal to pump current carriers (i.e., charge) into the device. Pumping is carefully controlled and should not be longer than 300 ns for a DSRD. When all of the pumped charge is pulled out of the enriched region, the current suddenly stops or breaks, and the voltage increases across the DSRD. The turn off time depends on the voltage. The rise time (i.e., dV/dt) is on the order of 1.0 kV/ns, and the turn off time is approximately 1.0 ns for a DSRD having a 1.0 kV operating voltage. A DSRD has significantly better thermal stability than an SRD. Several DSRDs (e.g., tens and hundreds of DSRDs) can be assembled in series in a stack with relative ease. Due to negligible loss of pumping charge, all of the DSRDs in the stack break current essentially simultaneously. An output pulse, therefore, can be increased in orders of magnitude while providing the same short front pulse characteristic a single DSRD provides. Due to very short time the DSRD is under high voltage, the DSRD is not sensitive to leakage current. A DSRD is described in Russian patent SU 1581149 A1 for "High Voltage Diode Having Sharp Recovery". A drift step recovery transistor (DSRT) is described in Russian patent SU 1783606 A1 for "Methods of Generation of Voltage Steps".
FIG. 1 depicts a pulse generating circuit discussed in the above-referenced paper that comprises a DSRD, and FIG. 2 illustrates selected waveforms for the circuit. Initially, energy storage capacitors C1 and C2 are charged, and switches S1 and S2 are open. When switch S1 is closed, capacitor C1 discharges via an inductor L1 and the DSRD. Because of the capacitor polarity, the discharge current is forward current for the DSRD. The resistance of the DSRD is low, and the current I1 oscillates in the circuit comprising C1, S1, L1 and the DSRD. The total amount of electron-hole pairs injected or pumped into the DSRD during the first forward half-cycle of current is essentially equal to the charge passing through the DSRD. When the current changes direction on the next half-cycle, the DSRD remains in a high conducting state because of the stored electron-hole pairs. If switch S2 closes at the moment the current I1 crosses zero-level, discharge current I2 through the capacitor C2 is added to the L1, C1 circuit such that the total DSRD current is increased. When the current through the DSRD is maximum, the charge extracted for the .tau..sub.-- time period is essentially equal to the charge injected for the .tau..sub.-- period. Accordingly, the DSRD breaks current, and the energy initially stored in the capacitors C1 and C2 and accumulated in the inductors L1 and L2 is applied to the load resistance R1.
The front of the load pulse 11 generated by the circuit in FIG. 1 is determined by the turn off time of the DSRD, and the decay time is approximately L/R1 where L is the total inductance of L1 and L2 connected in parallel. The peak load voltage can be many times higher (e.g., on the order of ten times higher) than the initial capacitor voltage. This voltage multiplication is one of a number of advantages of circuits comprising a DSRD. The circuit, however, is disadvantageous because it employs switches S1 and S2 to charge the capacitors. The pulse repetition frequency is not more than 100 kilohertz (kHz) due to the relatively long period of time required to charge the capacitors and the relatively long recovery time of the switches. The use of additional switches for charging the capacitors makes the pulse generating circuit less reliable and more complicated. Another pulse generating circuit, which comprises a drift step recovery transistor (DSRT), eliminates the need to employ capacitors and switches. With reference to FIG. 3, the circuit comprises a direct current (DC) source 13 that is switched to the inductor L via the DSRT following a triggering pulse generated across the secondary winding of a transformer TXFR. The DSRT is pumped during the triggering pulse, and, when the DSRT current breaks, the inductor voltage is applied across a load resistor R. Thus, the pulse repetition frequency is controlled by the pumping time. The output voltage is limited by the transistor voltage.